In most conventional processors, a PLL located on the processor chip and an external reference clock are used to provide the processor clock. Typically, the reference clock has a frequency less than the frequency desired for the processor clock. For example, in a PCI system, the reference clock might have a frequency of either 33 megahertz ("MHz") or 66 MHz. The PLL uses the reference clock as a base and synthesizes a higher frequency signal to provide the clock for the microprocessor.
A processor using a PLL and a reference clock provides a processor clock which can be synchronous with the remainder of the system. This is because all components of the system, including the processor, can be aligned with an edge of the reference clock signal. However, a system using a PLL to synthesize the processor clock is generally susceptible to noise. For example, a PLL typically has a three sigma jitter, which is usually around 100 picoseconds.
A high speed processor clock with less jitter can be produced using a differential SAW. The SAW is located off of the processor, thereby reducing the background noise to which the clock is subject. The SAW also contains a narrow band filter which rejects noise outside of the band. Because of the narrow band filter, the SAW provides a single frequency signal. This single frequency signal is a sine wave. All harmonics and other effects seen in a noisy spectrum are thereby eliminated. As a result, less noise is fed into processor chip, thereby reducing the uncertainty in clock edge.
The differential SAW provides a first sine wave and a second sine wave 180 degrees out of phase with the first sine wave. Both sine waves have the single frequency passed by the narrow band filter inside the SAW. As discussed above, signals of other frequencies are eliminated. Although jitter is reduced, the duty cycle can be corrupted. Typically, the duty cycle will be corrupted by one of the sine waves being offset with respect to the other. If the clock is to function effectively, this offset must be corrected. In addition, it would be beneficial if the means for correcting the offset were relatively simple, requiring less circuitry.
Accordingly, what is needed is a system and method for providing a receiver which for corrects the duty cycle of a high speed differential signal. The present invention addresses such a need.